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@gcu/rv

v0.1.0

Published

RV32IMA RISC-V system emulator. Atra-compiled Wasm CPU core + JS host (ELF loader, DTB, UART console, Web Worker wrapper). Capable of booting a Linux kernel.

Vulnerabilities

Powered byPowered by Snyk
  • 0High
  • 0Medium
  • 0Low

Links

Git

Maintainers

endarthurendarthur

Keywords

risc-vrv32imaemulatorcpuwasmatralinuxauditablegcu

Readme

@gcu/rv

RV32IMA RISC-V system emulator. Atra-compiled Wasm CPU core + JavaScript host (ELF loader, DTB, UART console, Web Worker wrapper). Capable of booting a Linux kernel. See SPEC.md for details.

Part of Auditable.

Pre-1.0 — APIs may break on minor version bumps.

Install

npm install @gcu/rv

Usage

import { createMachine } from '@gcu/rv';

const mach = createMachine({ memSize: 64 * 1024 * 1024 });
await mach.loadELF(kernelBytes);
await mach.loadDTB(dtbBytes);
mach.run();

Worker variant at sub-path @gcu/rv/worker — launch in a Web Worker to keep the main thread responsive.

License

MIT — see LICENSE.