MCC Melody dsPIC33A CLOCK

The Clock peripheral helps the user to easily configure System Clock frequency and other Clock Generator frequencies using MCC Melody User Interface.

Features

Clock Generators

• Supports multiple Clock Generators
• Each Clock Generator has
  • Selectable Clock Source
  • Clock Divider block
  • Fail safe clock monitors
  • A backup clock source

Phase Locked Loop(PLL) Blocks

• Supports multiple PLL Blocks
• Selectable Clock Source
• Fail safe clock monitors
• A backup clock source
• PLL OUT divider output
• PLL VCO divider output

Clock Generator and PLL Clock Sources

• RC oscillator (FRC)
• RC backup oscillator (BFRC)
• Internal Low Power RC Oscillator(LPRC)
• PLL OUT output
• PLL VCO divider output
• External/Primary Oscillator
• External Reference Input (REFI pin)

Changelog

All notable changes to this project will be documented in this file.

[1.3.1] - 2025-12-10

Bug Fixes

• CC16SCRIP-10204 :- Register View updates for displaying correct setting bit values

[1.3.0] - 2025-11-26

New Features

• CC16SCRIP-9944 :- Support for MotorBench and other dependent modules for Clock configurations
• CC16SCRIP-7218 :- Context attribute support for all ISRs

Bug Fixes

• CC16SCRIP-10063 :- Removal of "auto_psv"/"no_auto_psv" from the ISR attribute

[1.2.1] - 2025-10-06

New Features

• CC16SCRIP-10092 :- Performance Improvement

[1.2.0] - 2025-07-16

New Features

• CC16SCRIP-9917 :- dsPIC A Core Slowness - Upgrade the relevant modules to latest Automodule which are having performance bottlenecks.
• CC16SCRIP-9836 :- Support added for dependent libraries to configure clock generator frequencies
• CC16SCRIP-9735 :- Suppress Cppcheck MISRA-C:2012 Rule 8.4 Warning with Justified Deviation
• CC16SCRIP-9673 :- Always configure PLL1VCO to 800 MHz (maximum and recommended),PLL1O to 320 MHZ and PLL2VCO to 500 MHz , PLL2O to 200 MHz

Bug Fixes

• CC16SCRIP-9915 :- Clock generator selection for Clock Source appears to give wrong frequency when selecting PLLx VCO Divider output

[1.1.2] - 2025-05-08

New Features

• CC16SCRIP-9736 :- Suppress Cppcheck MISRA-C:2012 Rule 8.12 Warning with Justified Deviation
• CC16SCRIP-9066 :- Support for dsPIC33AK512MPSxxx family of devices
• CC16SCRIP-5987 :- Register Initialization View missing for system components,

[1.1.1] - 2025-04-01

New Features

• CC16SCRIP-9682 :- MCC Melody Application Builder not allowing clock fractional divide with Integer part=0
• CC16SCRIP-5985 :- Graphical UI Block diagram support for Clock Module

Bug Fixes

• CC16SCRIP-9672 :- Enable failsafe clock by default for clock generator 1
• CC16SCRIP-9654 :- System clock is switched to FRC if PLL clock is being used before making any changes to PLL settings
• CC16SCRIP-9640 :- Update the default value of BOSC to BFRC during the initialization stage
• CC16SCRIP-9617 :- Added #ifndef guard to not to execute clock switch and divider switch statements in simulator mode
• CC16SCRIP-9115 :- Clock: A core : In PLL Block , description added as part of "Notes" UI component is not clearly visible

[1.1.0] - 2024-07-18

New Features

• CC16SCRIP-8583 :- Initial version